RSQ opcode requires replicate swizzle.
--- a/mojoshader.c Mon Jul 20 16:14:43 2020 -0400
+++ b/mojoshader.c Mon Jul 20 18:53:54 2020 -0400
@@ -1504,6 +1504,12 @@
fail(ctx, "RCP without replicate swizzle");
} // state_RCP
+static void state_RSQ(Context *ctx)
+{
+ if (!replicate_swizzle(ctx->source_args[0].swizzle))
+ fail(ctx, "RSQ without replicate swizzle");
+} // state_RSQ
+
static void state_LOOP(Context *ctx)
{
if (ctx->source_args[0].regtype != REG_TYPE_LOOP)
--- a/mojoshader_assembler.c Mon Jul 20 16:14:43 2020 -0400
+++ b/mojoshader_assembler.c Mon Jul 20 18:53:54 2020 -0400
@@ -1254,7 +1254,8 @@
ctx->tokenbufpos = 0;
ctx->default_writemask = instruction->default_writemask;
- if (opcode == OPCODE_RCP) // RCP has an implicit swizzle of .xxxx if not specified.
+ // RCP and RSQ have an implicit swizzle of .xxxx if not specified.
+ if ((opcode == OPCODE_RCP) || (opcode == OPCODE_RSQ))
ctx->default_swizzle = 0; // .xxxx replicate swizzle.
const int tokcount = instruction->parse_args(ctx);
--- a/mojoshader_internal.h Mon Jul 20 16:14:43 2020 -0400
+++ b/mojoshader_internal.h Mon Jul 20 18:53:54 2020 -0400
@@ -413,6 +413,7 @@
// we need to reference these by explicit value occasionally...
#define OPCODE_RCP 6
+#define OPCODE_RSQ 7
#define OPCODE_RET 28
#define OPCODE_IF 40
#define OPCODE_IFC 41
@@ -781,7 +782,7 @@
INSTRUCTION(MAD, "MAD", 1, DSSS, MOJOSHADER_TYPE_ANY, 0xF)
INSTRUCTION(MUL, "MUL", 1, DSS, MOJOSHADER_TYPE_ANY, 0xF)
INSTRUCTION_STATE(RCP, "RCP", 1, DS, MOJOSHADER_TYPE_ANY, 0xF)
-INSTRUCTION(RSQ, "RSQ", 1, DS, MOJOSHADER_TYPE_ANY, 0xF)
+INSTRUCTION_STATE(RSQ, "RSQ", 1, DS, MOJOSHADER_TYPE_ANY, 0xF)
INSTRUCTION(DP3, "DP3", 1, DSS, MOJOSHADER_TYPE_ANY, 0xF)
INSTRUCTION_STATE(DP4, "DP4", 1, DSS, MOJOSHADER_TYPE_ANY, 0xF)
INSTRUCTION(MIN, "MIN", 1, DSS, MOJOSHADER_TYPE_ANY, 0xF)