Mon, 20 Jul 2020 16:14:43 -0400 The assembler needs to accept an implicit ".x" swizzle on RCP's source arg.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 16:14:43 -0400] rev 1290
The assembler needs to accept an implicit ".x" swizzle on RCP's source arg.
Mon, 20 Jul 2020 15:37:27 -0400 Minor replicate_swizzle optimization.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 15:37:27 -0400] rev 1289
Minor replicate_swizzle optimization. Do it in two tests instead of three, and with two shifts instead of five.
Mon, 20 Jul 2020 15:35:34 -0400 Clean up assembler writemask parsing a little.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 15:35:34 -0400] rev 1288
Clean up assembler writemask parsing a little.
Mon, 20 Jul 2020 15:18:14 -0400 List default writemasks for instructions.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 15:18:14 -0400] rev 1287
List default writemasks for instructions. This lets this line of assembly generate correct code: m3x3 r7, r4, c28 As this is legal, but the bytecode validator will throw it out for having a writemask of .xyzw on r7 when it requires .xyz. The assembler needs to know what the implicit writemask should be in this circumstance. (Some instructions might still be incorrect, but are left at the default of a full .xyzw writemask, so they continue to act as before until corrected.)
Mon, 20 Jul 2020 15:14:32 -0400 Fixed typo in error message.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 15:14:32 -0400] rev 1286
Fixed typo in error message.
Mon, 20 Jul 2020 14:54:14 -0400 Assembler now accepts "c[5]" as equivalent to "c5".
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 14:54:14 -0400] rev 1285
Assembler now accepts "c[5]" as equivalent to "c5". This only accepts a constant integers, you can't currently do something like "c[2+3]" even if the constants could be completely folded during assembly. I don't know if Microsoft's tools allow that, will have to revisit later if so.
Mon, 20 Jul 2020 14:52:00 -0400 Assembler now deals with scalar registers specifying a write mask better.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 14:52:00 -0400] rev 1284
Assembler now deals with scalar registers specifying a write mask better.
Mon, 20 Jul 2020 14:51:03 -0400 Don't make the MOJOSHADER_DO_INSTRUCTION_TABLE caller undef everything after.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 14:51:03 -0400] rev 1283
Don't make the MOJOSHADER_DO_INSTRUCTION_TABLE caller undef everything after.
Mon, 20 Jul 2020 14:50:10 -0400 For SM1.1 TEX, don't add texcoord attributes.
Ryan C. Gordon <icculus@icculus.org> [Mon, 20 Jul 2020 14:50:10 -0400] rev 1282
For SM1.1 TEX, don't add texcoord attributes. Other parts of the system will generate the tX registers as global variables, assign gl_TexCoord[X] to them, and overwrite them with the sampled pixels during the TEX instruction. Setting these as texcoord attributes causes it to _also_ generate a generic vertex attribute and cause all sorts of problems.
Sun, 19 Jul 2020 23:44:13 -0400 Correct the reported usage on SM1 vertex shader input registers.
Ryan C. Gordon <icculus@icculus.org> [Sun, 19 Jul 2020 23:44:13 -0400] rev 1281
Correct the reported usage on SM1 vertex shader input registers. They are hardcoded to mean specific things (v0 is POSITION0, v1 is BLENDWEIGHT, etc).
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